MBW=00, CURPIPE=Others, DCLRM=0, REW=0, DREQE=0, BIGEND=0, RCNT=0
D1FIFO Port Selection Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0x0): No pipe specification 0 (Others): Setting prohibited 1 (0x1): Pipe 1 2 (0x2): Pipe 2 3 (0x3): Pipe 3 4 (0x4): Pipe 4 5 (0x5): Pipe 5 6 (0x6): Pipe 6 7 (0x7): Pipe 7 8 (0x8): Pipe 8 9 (0x9): Pipe 9 |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| MBW | FIFO Port Access Bit Width 0 (00): 8-bit width 1 (01): 16-bit width 2 (10): 32-bit width 3 (11): Setting prohibited |
| DREQE | DMA/DTC Transfer Request Enable 0 (0): Disable DMA/DTC transfer request 1 (1): Enable DMA/DTC transfer request |
| DCLRM | Auto FIFO Buffer Clear Mode after Specified Pipe is Read 0 (0): Disable auto buffer clear mode 1 (1): Enable auto buffer clear mode |
| REW | Buffer Pointer Rewind 0 (0): Do not rewind buffer pointer (writing 0 has no effect) 1 (1): Rewind buffer pointer |
| RCNT | Read Count Mode 0 (0): Clear DTLN[11:0] flags in the FIFO port control register to 0x000 when all receive data is read from DnFIFO (after read of a single plane in double buffer mode) 1 (1): Decrement DTLN[11:0] flags each time receive data is read from DnFIFO |